Field
The described embodiments relate to reducing latency on a data link. More specifically, the described embodiments relate to reducing latency on a peripheral component interconnect express link between an endpoint and a host.
Related Art
Many modern computer systems use a peripheral component interconnect express (PCIe) link to communicate between a host and an endpoint. When a PCIe link is unused for a period of time, an endpoint may try to save power by putting the PCIe link into a power-saving mode. Typically, the more power that is saved by a power-saving mode, the longer the amount of time it takes for the PCIe link to exit the power-saving mode and become operational again.
When an operating system on a host tries to communicate with an endpoint over a PCIe link that is in a power-saving mode, the operating system will have to wait for the PCIe link to exit the power-saving mode to allow communication between the host and the endpoint to resume. This delay while waiting for the PCIe link to resume may exceed the allowable delay tolerances for some operating systems, resulting in unexpected or unacceptable behavior and possibly an undesirable user experience.
In the figures, like reference numerals refer to the same figure elements.